PLTRST #
O The total reset signal: PLTRST # is the Intel ® ICH9 always reset the whole platform (such as: I / O, BIOS chip, card, north bridge, etc.). During the power up and when S / W signal through the reset control register (I / O registers CF9h) to initialize a hard reset sequence PLTRST # ICH9 determine the status. In PWROK and VRMPWRGD is high after the ICH9 driver PLTRST # at least 1 millisecond is invalid. When initialized by resetting the control register (I / O registers CF9h) when the ICH9 driver PLTRST # at least 1 ms to be effective.
Note: OnlyVccSus3_3 normal PLTRST # This signal is applied. THRM # I Thermal alarm signal:THRM # is low active signal to the external hardware to generate an SMI # or SCI signal THRMTRIP #
I Thermal circuit signal: When THRMTRIP # signal for the low type, the heat from the processor circuit model, ICH9 immediately converted to S5 state. ICH9 will not wait for the grant from the processor to stop the signal to return will go to the S5 state. SLP_S3 # O S3 Sleep Control signal: SLP_S3 # is the power level control.
When entering the S3 (Suspend to RAM), S4 (suspend to disk), S5 (soft off) state, the signal to switch off all non-critical system power. SLP_S4 # O S4 Sleep control signal: SLP_S4 # i is the power level control signal. When entering the S4 (Suspend to disk), S5 (soft off) state when the signal to switch off all non-critical system power.
Note: ThisPinPreviously used to control footICH9’s DRAM power circulation.
Note:In a system supported on Intel’s AMT, the signal used to control the DRAM power supply,
Notes:In the M1 state (when the host is in S3, S4, S5 state and operational sub-system running state) the signal is forced high with SLP_M # to the DIMM provide sufficient power for the operational subsystem. SLP_S5 # O S5 Sleep Control signal: SLP_S5 # is a power level control signal. When the system into the S5 (soft off) state SLP_S5 # shut down the system for all non-critical power. SLP_M # O Operational sleep control signal:Intel AMT for power level control subsystem. If you do not exist for the engine firmware, SLP_M # will SLP_S3 # synchronization. S4_STATE # / GPIO26
O S4 state pointer signal:When the machine is in S4 or S5 state, the signal is active low. When the machine is operable in the S3 state, the engine force SLP_S4 # with SLP_S4 # is high, this signal can be used for other devices to understand the current state of the machine
PWROK I Power normal signal:All power distribution bus and PCICLK stable steady 99ms 1ms time, PWROK to the South Bridge a valid symbol. . PWROK can asynchronously drive. PWROK low the southbridge will think PLTRST # effective.
Note: 1. In the normal three RTC clock cycle Southbridge to completely reset the power and generate a complete PLTRST # signal output, PWROK must be a minimum of an invalid state.
2. PWROK must be no false signals, even if RSMRST # is low. CLPWROK
I ControlLINKPower normal signal:WhenCLPWROKEffectively, it said that from theLINK power to control subsystem (Northbridge, Southbridge, etc.) is stable and the South Bridge to CL_RST # invalid notice until the North Bridge received the signal
NOTES: 1. RSMRST # invalid before the CLPWROK allowed effective.
2, effective after the CLPWROK allowed in PWROK effective.
PWRBTN # I Power button:. The power button will cause SMI # or SCI to indicate a sleep state of the system. If the system is already sleeping, then this signal will trigger a wake-up event. If PWRBTN # valid for more than 4s, regardless of the system in the S0, S1, S3, S4 state, then the state will unconditionally transition to S5. This signals an internal input pull-up resistor and an internal of 16ms debounce design.
RI # I Ringtones Tip: This signal is an input signal from the Modem. It allows a wake-up event, the time in power failure protection SYS_RESET # I System reset: After the signal anti-rebound force an internal reset. If the SMBus is idle, South Bridge will soon reset, also forced a reduction in the system before, SYS_RESET # will wait until the SMBus idle 25ms ± 2ms
RSMRST # I Restoration of a normal reset signal:
This signal is used to reset the power to restore the logic, all power is effectively the signal will work at least 10ms, when the lifting of valid, the signal is hang a sign of stability in the bus LAN_RST # I LAN Reset:
When the signal valid when the internal controller to reset the LAN, the LAN’s ccLAN3_3 and VccLAN1_05 and VccCL3_3 normal state of the signal power to be effective. When the lifting of valid, this signal is a sign of stability LAN busNote: 1. RSMRST # LAN_RST # must be lifted before it can be effective.
2. PWROK effective after, LAN_RST # must be valid.
Three. VccLAN1_05 and VccCL3_3 in VccLAN3_3 and power are normal circumstances LAN_RST # must be valid 1ms.
4. If the integrated network card LAN_RST # can not connect it to the Vss. WAKE # I PCI Express * wake-up events:Sideband wake signal on PCI Express slot and issue a wake-up request signal components MCH_SYNC # I North Bridge sync signal:The input signal is a phase with PWROK internally, and the signal connected to the North Bridge ICH_SYNC # output.
SUS_STAT # / LPCPD # O Suspend status signal:Effective immediately the signal that the system to enter low-power state. It can monitor these devices, and memory from the normal mode into suspend mode, it can be used to isolate the output of other peripheral devices and turn off their power, the signal in the LPC I / F call LPCPD # achieved. SUSCLK O Hang clock signal:This clock is the RTC clock generator produced by other chip clock output. VRMPWRGD I CPUPower normal signal:This signal is connected directly to the CPU power management chips, the normal signal that VRM is stable. The input signal is the phase of the internal PWROK.
When the signal is normal in the pending CK_PWRGD O Clock pulse generator power normal signal: When the main power and effective when the signal to clock generator, when SLP_S3 # and VRMPWRGD two signals are high when the signal is as high effective PMSYNC # (Only for laptop) / GPIO0 O Sync signal power management:When the signal effectively, C5 or C6 in the exit when the signal from the North Bridge to CPUSLP # this pin is invalid.
This signal can also be used for GPIO.
CLKRUN # (Only for laptop) / GPIO32 (only for desktop computers) I / O PCI clock run signal: This signal is used to support PCI
CLKRUN agreement. When connected to an external device for restarting the clock when the clock stop or prevent
STP_PCI # / GPIO15 (only for desktop computers) O close the PCI clock signal: When STP_PCI # signal is low when the external clock pulse generator will turn off PCI clock signal. It previously used in notebook computers up to support PCI CLKRUN # agreement.
In Sx (S0, S1, S3, S4, S5) state, when the system will open the Intel AMT or ASF, in order to support the Moff / Sx to M1/Sx conversion, this pin is used to inform the clock controller, select the main clock frequency.
The desktop platform, the signal can be converted into GPIO signal, then it would not support Intel AMT or ASF. STP_CPU # / GPIO25 (only for desktop computers) O block the CPU clock signal: the signal will effectively turn off the CPU clock generator command external clock, the laptop computer used to support the C3 state. In Sx (S0, S1, S3, S4, S5) state, when the system will open the Intel AMT or ASF, in order to support the Moff / Sx to M1/Sx conversion, this pin is used to inform the clock controller, select the main clock frequency.
The desktop platform, the signal can be converted into GPIO signal, then it do not support Intel AMT or ASF. BATLOW # (only for laptop) / TP0 (only for desktop computers) I battery low signal: This input signal from the notebook battery when the battery is not sufficient to maintain the system to send a signal. This signal effectively prevents the system from when it is S3, S4, S5 wake up, it can cause a SMI # signal effectively. DPRSLPVR (only for laptop) / GPIO16 O deeper sleep – Regulators signal: the signal for the VRM in the C4 state, the voltage drop even lower. When this signal is high, the regulator output voltage is less deep sleep. When the signal is low (default is low), the normal voltage regulator output. (Voltage regulator that VRM) DPRSTP # (only for laptop) / TP1 (only for desktop computers) O the depth stop signal: This is a copy DPRSLPVR signal, active low.
O The total reset signal: PLTRST # is the Intel ® ICH9 always reset the whole platform (such as: I / O, BIOS chip, card, north bridge, etc.). During the power up and when S / W signal through the reset control register (I / O registers CF9h) to initialize a hard reset sequence PLTRST # ICH9 determine the status. In PWROK and VRMPWRGD is high after the ICH9 driver PLTRST # at least 1 millisecond is invalid. When initialized by resetting the control register (I / O registers CF9h) when the ICH9 driver PLTRST # at least 1 ms to be effective.
Note: OnlyVccSus3_3 normal PLTRST # This signal is applied. THRM # I Thermal alarm signal:THRM # is low active signal to the external hardware to generate an SMI # or SCI signal THRMTRIP #
I Thermal circuit signal: When THRMTRIP # signal for the low type, the heat from the processor circuit model, ICH9 immediately converted to S5 state. ICH9 will not wait for the grant from the processor to stop the signal to return will go to the S5 state. SLP_S3 # O S3 Sleep Control signal: SLP_S3 # is the power level control.
When entering the S3 (Suspend to RAM), S4 (suspend to disk), S5 (soft off) state, the signal to switch off all non-critical system power. SLP_S4 # O S4 Sleep control signal: SLP_S4 # i is the power level control signal. When entering the S4 (Suspend to disk), S5 (soft off) state when the signal to switch off all non-critical system power.
Note: ThisPinPreviously used to control footICH9’s DRAM power circulation.
Note:In a system supported on Intel’s AMT, the signal used to control the DRAM power supply,
Notes:In the M1 state (when the host is in S3, S4, S5 state and operational sub-system running state) the signal is forced high with SLP_M # to the DIMM provide sufficient power for the operational subsystem. SLP_S5 # O S5 Sleep Control signal: SLP_S5 # is a power level control signal. When the system into the S5 (soft off) state SLP_S5 # shut down the system for all non-critical power. SLP_M # O Operational sleep control signal:Intel AMT for power level control subsystem. If you do not exist for the engine firmware, SLP_M # will SLP_S3 # synchronization. S4_STATE # / GPIO26
O S4 state pointer signal:When the machine is in S4 or S5 state, the signal is active low. When the machine is operable in the S3 state, the engine force SLP_S4 # with SLP_S4 # is high, this signal can be used for other devices to understand the current state of the machine
PWROK I Power normal signal:All power distribution bus and PCICLK stable steady 99ms 1ms time, PWROK to the South Bridge a valid symbol. . PWROK can asynchronously drive. PWROK low the southbridge will think PLTRST # effective.
Note: 1. In the normal three RTC clock cycle Southbridge to completely reset the power and generate a complete PLTRST # signal output, PWROK must be a minimum of an invalid state.
2. PWROK must be no false signals, even if RSMRST # is low. CLPWROK
I ControlLINKPower normal signal:WhenCLPWROKEffectively, it said that from theLINK power to control subsystem (Northbridge, Southbridge, etc.) is stable and the South Bridge to CL_RST # invalid notice until the North Bridge received the signal
NOTES: 1. RSMRST # invalid before the CLPWROK allowed effective.
2, effective after the CLPWROK allowed in PWROK effective.
PWRBTN # I Power button:. The power button will cause SMI # or SCI to indicate a sleep state of the system. If the system is already sleeping, then this signal will trigger a wake-up event. If PWRBTN # valid for more than 4s, regardless of the system in the S0, S1, S3, S4 state, then the state will unconditionally transition to S5. This signals an internal input pull-up resistor and an internal of 16ms debounce design.
RI # I Ringtones Tip: This signal is an input signal from the Modem. It allows a wake-up event, the time in power failure protection SYS_RESET # I System reset: After the signal anti-rebound force an internal reset. If the SMBus is idle, South Bridge will soon reset, also forced a reduction in the system before, SYS_RESET # will wait until the SMBus idle 25ms ± 2ms
RSMRST # I Restoration of a normal reset signal:
This signal is used to reset the power to restore the logic, all power is effectively the signal will work at least 10ms, when the lifting of valid, the signal is hang a sign of stability in the bus LAN_RST # I LAN Reset:
When the signal valid when the internal controller to reset the LAN, the LAN’s ccLAN3_3 and VccLAN1_05 and VccCL3_3 normal state of the signal power to be effective. When the lifting of valid, this signal is a sign of stability LAN busNote: 1. RSMRST # LAN_RST # must be lifted before it can be effective.
2. PWROK effective after, LAN_RST # must be valid.
Three. VccLAN1_05 and VccCL3_3 in VccLAN3_3 and power are normal circumstances LAN_RST # must be valid 1ms.
4. If the integrated network card LAN_RST # can not connect it to the Vss. WAKE # I PCI Express * wake-up events:Sideband wake signal on PCI Express slot and issue a wake-up request signal components MCH_SYNC # I North Bridge sync signal:The input signal is a phase with PWROK internally, and the signal connected to the North Bridge ICH_SYNC # output.
SUS_STAT # / LPCPD # O Suspend status signal:Effective immediately the signal that the system to enter low-power state. It can monitor these devices, and memory from the normal mode into suspend mode, it can be used to isolate the output of other peripheral devices and turn off their power, the signal in the LPC I / F call LPCPD # achieved. SUSCLK O Hang clock signal:This clock is the RTC clock generator produced by other chip clock output. VRMPWRGD I CPUPower normal signal:This signal is connected directly to the CPU power management chips, the normal signal that VRM is stable. The input signal is the phase of the internal PWROK.
When the signal is normal in the pending CK_PWRGD O Clock pulse generator power normal signal: When the main power and effective when the signal to clock generator, when SLP_S3 # and VRMPWRGD two signals are high when the signal is as high effective PMSYNC # (Only for laptop) / GPIO0 O Sync signal power management:When the signal effectively, C5 or C6 in the exit when the signal from the North Bridge to CPUSLP # this pin is invalid.
This signal can also be used for GPIO.
CLKRUN # (Only for laptop) / GPIO32 (only for desktop computers) I / O PCI clock run signal: This signal is used to support PCI
CLKRUN agreement. When connected to an external device for restarting the clock when the clock stop or prevent
STP_PCI # / GPIO15 (only for desktop computers) O close the PCI clock signal: When STP_PCI # signal is low when the external clock pulse generator will turn off PCI clock signal. It previously used in notebook computers up to support PCI CLKRUN # agreement.
In Sx (S0, S1, S3, S4, S5) state, when the system will open the Intel AMT or ASF, in order to support the Moff / Sx to M1/Sx conversion, this pin is used to inform the clock controller, select the main clock frequency.
The desktop platform, the signal can be converted into GPIO signal, then it would not support Intel AMT or ASF. STP_CPU # / GPIO25 (only for desktop computers) O block the CPU clock signal: the signal will effectively turn off the CPU clock generator command external clock, the laptop computer used to support the C3 state. In Sx (S0, S1, S3, S4, S5) state, when the system will open the Intel AMT or ASF, in order to support the Moff / Sx to M1/Sx conversion, this pin is used to inform the clock controller, select the main clock frequency.
The desktop platform, the signal can be converted into GPIO signal, then it do not support Intel AMT or ASF. BATLOW # (only for laptop) / TP0 (only for desktop computers) I battery low signal: This input signal from the notebook battery when the battery is not sufficient to maintain the system to send a signal. This signal effectively prevents the system from when it is S3, S4, S5 wake up, it can cause a SMI # signal effectively. DPRSLPVR (only for laptop) / GPIO16 O deeper sleep – Regulators signal: the signal for the VRM in the C4 state, the voltage drop even lower. When this signal is high, the regulator output voltage is less deep sleep. When the signal is low (default is low), the normal voltage regulator output. (Voltage regulator that VRM) DPRSTP # (only for laptop) / TP1 (only for desktop computers) O the depth stop signal: This is a copy DPRSLPVR signal, active low.